Mastering FPGA System Design with Verilog and RISC-V Implementation ( 4 + 2 Weeks:)
Module 2: Deep Dive into Verilog HDL for RTL Design and Verification
- Verilog Fundamentals
- Data Types and Operators in Verilog
- Blocking vs. Nonblocking Statements
- Behavioral Modeling Techniques
- Combinational and Sequential Logic Design
- Synthesizable RTL Design Principles
- RTL Coding Guidelines
- Timing Controls in RTL Design
- Compiler Directives and System Tasks
- Tasks and Functions in Verilog
- Modeling Delays in Verilog
- Effective Verification Strategies in Verilog
- File I/O Operations in Testbenches
- Self-Checking Testbench Constructs
- Real-World Applications and Case Studies
Module 3. RTL Design and Verification of RISC-V using Verilog
- Overview of RISC-V Architecture
- Setting Up the Design Environment RISC-V project structure
- ALU Design and Implementation for RISC-V Core
- Register File and Control Logic
- Memory and Data Path Integration
- Branching and Control Flow Instructions
- Load and Store Operations
- Synthesis and Timing Analysis
- Writing effective Verilog testbenches for RISC-V verification
- Creating Functional Tests for RISC-V Instructions
- Debugging and Simulation
Prerequisites:
Basic knowledge of digital logic design.
Course Fee:
₹12,500 + 18% GST
Tools Used:
Development board :EDGE Artix 7
RTL Design and Simulation :Verilator, Icarus Verilog, GTKWave
Sysnthesis & Implementation:Xilinx Vivado
Advanced Verilog: Mastering On-Chip Protocols (AMBA APB, AXI, AXIS, AXI-Lite) (6 Weeks: 4 + 2)
Module 2: Comprehensive RTL Design and Verification of On-Chip Protocols: AMBA APB, AXI, AXIS, and AXI-Lite using Verilog
- Introduction to On-Chip Protocols - APB, AXI, AXIS, and AXI-Lite
- AMBA APB Protocol - RTL Design and Verification
- AMBA AXIS Protocol - RTL Design and Verification
- AXI-Lite Protocol - RTL Design and Verification
- System-Level Integration of On-Chip Protocols
- Capstone Project and Documentation
Prerequisites:
Basic knowledge of digital logic design.
Course Fee:
₹12,500 + 18% GST
Tools Used:
Development board : EDGE Artix 7
RTL Design and Simulation :Verilator, Icarus Verilog, GTKWave
Sysnthesis & Implementation:Xilinx Vivado
Advanced Verilog: Mastering Off-Chip Protocols (UART, SPI, & I2C) (6 Weeks: 4 + 2)
Module 2: Mastering Off-Chip Protocols (UART, SPI, & I2C) - Design and Verification using I2C protocol using Verilog HDL
- Overview of Off-Chip Protocols: Understanding UART, SPI, and I2C in embedded systems and SoCs
- Protocol Comparison: Key differences in data transfer, speed, and applications
- Basics of UART Communication: Data framing, baud rate, parity, start/stop bits, and flow control
- UART Operation Modes: Full-duplex and half-duplex communication
- UART Design Considerations: Implementing error handling, baud rate generation, and data framing
- Introduction to SPI Protocol: Data transfer using MOSI, MISO, SCK, and SS signals
- SPI Modes and Configuration: Clock polarity, clock phase, and bit ordering
- Multi-Slave Communication: Using chip select lines for multiple slave devices
- Understanding I2C Protocol: Data/address format, start/stop conditions, and acknowledgment
- I2C Operation Modes: Master, slave, multi-master, and clock stretching
- Addressing and Arbitration: Using 7-bit and 10-bit addressing, handling arbitration
- I2C Master Design in Verilog
- I2C Slave Design in Verilog
- I2C Testbench Development and Verification
- Structured Testbench: Architecture for I2C verification
- Test Scenarios: Single/multi-byte read/write, clock stretching, arbitration
- Self-Checking: Automate verification with self-checks
- Documentation: Report design, test results, insights
- Presentation: Demonstrate I2C system and discuss challenges
Prerequisites:
Basic knowledge of digital logic design.
Course Fee:
₹12,500 + 18% GST
Tools Used:
Development board :EDGE Artix 7
RTL Design and Simulation :Verilator, Icarus Verilog, GTKWave
Sysnthesis & Implementation:Xilinx Vivado
Mastering RTL-to-GDS Implementation of a RISC-V Processor Using Open-Source EDA Tools
Module 2: RTL-to-GDS Implementation of a RISC-V Processor Using Open-Source EDA Tools
- Introduction to RISC-V Architecture and Open-Source EDA Tools
- RTL Design of a RISC-V Core
- RTL Synthesis with Yosys
- Floorplanning and Placement with OpenROAD
- Clock Tree Synthesis (CTS)
- Routing and Layout Optimization
- Physical Verification with Magic and Open-Source Tools
- Timing Analysis and Optimization
- Power Analysis and Optimization
- Generating GDSII and Tape-Out Preparation
- Capstone Project
- Course Wrap-Up
Prerequisites:
Basic knowledge of digital logic design.
Course Fee:
₹17,500 + 18% GST
Tools Used:
RTL Design and Simulation :Verilator, Icarus Verilog, GTKWave
Logic Synthesis:Yosys (with ABC for optimization)
Floorplanning, Placement, and Routing:OpenROAD
Static Timing Analysis (STA):OpenSTA
Physical Verification (DRC and LVS):Magic, KLayout
Power Analysis:OpenROAD (integrated power analysis)
GDSII Generation and Layout Finishing:Magic, KLayout
Deep Dive into SystemVerilog with Hands-On Projects (6 + 2 Weeks)
Module 2:AMBA APB I2C Verification using System Verilog
- Introduction to Protocols - AMBA Protocols: I2C, AMBA AHB,and APB
- Interfacing and Architecture Design -Interfacing APB with I2C
- Driver Development - SystemVerilog Driver for AMBA APB, I2C
- Monitor and Coverage Collection
- Transaction-Level Modeling and Sequences
- Building and Integrating the Test Environment
- Advanced Scenarios and Error Injection
- Coverage Analysis and Verification Closure
- Debugging, Simulation, and Final Review
Prerequisites:
Basic knowledge of digital logic design, Verilog HDL
Course Fee:
₹19,500 + 18% GST
Tools Used:
Development board : EDGE Artix 7
RTL Design and Simulation :EDA PG (VCS, Xielium, Questasim)
Sysnthesis & Implementation:Xilinx Vivado
