• Number Systems and Conversions
• Combinational Circuits - Design and Analysis
• Sequential Circuits – Counters, Shift Registers, Sequence Detectors - Design and Analysis
• Timing Parameters
• Finite State Machines

• Introduction to CMOS Technology
• CMOS Fundamentals
• CMOS Invertor Characteristics
• CMOS Fabrication Process
• CMOS Circuit Design Basics
• CMOS Power Consumption
• Low Power Design Techniques

• Introduction to UNIX-based Systems
• Directory Structure and File System Navigation
• Essential Utilities and Commands
• Introduction to Vi Text Editor
• Introduction to Version Control System
• Git Basics
• Branching and Merging
• Collaborative Development with Git
• Git Workflows in EDA Projects
• Git for Bug Tracking and Issue Management

• Verilog Fundamentals
• Data Types and Operators in Verilog
• Blocking vs. Nonblocking Statements
• Behavioral Modeling Techniques
• Combinational and Sequential Logic Design
• Synthesizable RTL Design Principles
• RTL Coding Guidelines
• Timing Controls in RTL Design
• Compiler Directives and System Tasks
• Tasks and Functions in Verilog
• Modeling Delays in Verilog
• Effective Verification Strategies in Verilog
• File I/O Operations in Testbenches
• Self-Checking Testbench Constructs
• Real-World Applications and Case Studies

• Introduction to Static Timing Analysis (STA)
• Timing Path and Constraints
• Different Types of Clocks and Clock Domains
• Timing Exceptions
• How to Fix Timing Failure
• STA Issues and Solutions
• Methods to Improve Timing

• Introduction to Perl Programming
• Perl Functions and Statements
• Numbers, Strings, and Quotes in Perl
• Comments, Loops, and Control Structures
• Regular Expressions in Perl
• File Operations and Data Processing
• Mini Project – Realtime case studies

• Functional Verification Overview
• Introduction to SystemVerilog
• Procedural Statements and Arrays
• Mailbox, Packages, Compilation Unit
• Object-Oriented Programming and Randomization
• Fork-Join and Inter-Process Synchronization (Threads)
• Program and Clocking Block
• Tasks and Functions in SystemVerilog
• Virtual Interfaces and Building Verification Environment
• Constraining and Randomization Techniques
• Advanced Data Types in SystemVerilog
• Direct Programming Interface (DPI)
• Functional and Code Coverage Analysis
• Regression Testing Strategies

• UVM Basics
• Revisit OOP Basics
• Testbench Architecture
• DUT-Testbench Connections
• Configuring a Test Environment
• Analysis Components & Techniques
• Sequences – Virtual Sequences
• Transaction Level Modeling
• The UVM Messaging System
• Register Abstraction Layer
• Debug of SV and UVM
• UVM Connect - SV-SystemC interoperability

• Memory Access Protocols
• Asynchronous FIFO Design
• Handling Clock Domain Crossing issues
• AMBA Protocol Overview – AXI, AXIS, AXIL, APB
• Mini Project: Design and Verification Using Memories Peripherals and AXI
• UART Protocol
• I2C Protocol
• SPI Protocol

• AXI Protocol basics and Advanced Concepts
• AXI VIP (Verification IP) Introduction
• AXI VIP Operation and Configuration
• Testbench Development for AXI Protocol
• AXI Protocol Interfacing and Integration
• Real-World Applications and Case Studies

• Introduction to Assertion-Based Verification (ABV)
• Immediate Assertions
• Simple Assertions
• Sequences and Sequence Composition
• Advanced SVA Features
• Assertion Coverage
• Advanced Applications and Case Studies

• Verification Plan Development
• Testbench (TB) Architecture Design
• Coverage Model and Analysis
• Simulation Process Tracking and Management
• Building Regression Test Suite
• Test Suite Optimization and Scalability

• Transition from College to Corporate
• Interpersonal Skills and Effective Presentation
• Email Etiquette and Professional Writing
• Resume Writing and Job Application Skills
• Mock Interviews: Technical and HR Rounds
• Interview Skills: Group Discussions and HR Round Preparation

• Verification and RTL Sign-off
• Project Specification Analysis
• Defining Verification Plan
• Creating Testbench Architecture
• Implementing Transactors
• Defining Transactions
• Implementing the Coverage Model
• Building the Top-Level Verification Environment
• Building Regression Test Suite
• Coverage Analysis and Coverage Closure
• Documentation and Project Presentation

(Internship with Industry: A Practical Application of VLSI Expertise)

• Design Specification Analysis
• Creating the Design Architecture
• Partitioning the Design
• RTL Coding in Verilog
• RTL Functional Verification
• RTL Synthesis
• Building Regression Test Suite
• Coverage Analysis and Coverage Closure
• Documentation and Project Presentation

Note: Assignments, tests, and interviews will be conducted in conjunction with each course module

I. Aptitude Tests - 10 Tests
Rigorous Aptitude Assessments to Gauge Problem-Solving Skills and Analytical Abilities

II. Assignments, Technical Tests, and Interviews
Advanced Digital Systems:
Assessing Knowledge in Complex Digital System Design and Analysis
CMOS Basics:
Evaluating Fundamental Understanding of CMOS Technology and Applications
Essentials of Linux for Electronic Design Automation:
Testing Proficiency in Linux Environment and EDA Tools Utilization
Advanced Verilog for RTL Design and Verification:
Practical Assessment of Verilog Skills for RTL Design and Verification
Static Timing Analysis
Evaluating Mastery in Timing Analysis Concepts and Techniques
Perl Scripts for Electronic Design Automation (EDA)
Assessing Scripting Skills for Automation in EDA Processes
ASIC Verification Methodologies:
Testing Knowledge of ASIC Verification Approaches and Strategies
SystemVerilog for Verification:
In-Depth Assessment of SystemVerilog Proficiency for Verification Tasks
UVM (Universal Verification Methodology)
Evaluation of UVM Expertise in Verificaion Environments
Essential Off-Chip Protocols for RTL Design and Verification (AMBA AXI, UART, I2C, SPI):
Proficiency Evaluation in Key Off-Chip Protocols for VLSI Communication
Essential On-Chip Protocols for RTL Design and Verification (AMBA APB, AXIS, AXIL, AXI)
In-Depth Understanding and Application of On-Chip Protocols
Advanced SystemVerilog for Verification
Advanced SystemVerilog Skills Evaluation for Complex Verification Challenges
Assertion-Based Verification - SVA (SystemVerilog Assertions)
Assessment of SVA Knowledge and Application in Verification
Verification Planning and Management
Evaluation of Verification Planning Skills and Management Strategies